A multi-bit delta-sigma modulator with a passband tunable from DC to half the sampling frequency.
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Word Count
25,500 words, Guess
Page Count
102 pages
Identifiers
- ISBN-139780494274668
- ISBN-100494274662
- Open LibraryOL21219027M
Description
The analysis and design of a discrete-time fully-tunable multi-bit delta-sigma modulator are presented in this thesis. The fourth-order CRFF (Cascade of resonators with feedforward) structure is employed with a four-bit quantizer whose nonlinearity is compensated using digital correction. The design of a tunable delta-sigma modulator for an integrated-circuit (IC) implementation involves some challenges such as coefficient quantization and the realization of coefficient programmability. The tunable modulator was designed and fabricated in the 0.18-mum CMOS technology. A peak SNDR of 96 dB was achieved at an OSR of 96 (270-kHz bandwidth) with a sampling frequency of 50 MHz and 108-mW power consumption was achieved for configurations from the lowpass configuration to the highpass configuration through the bandpass configuration based on the simulation results. These simulated results suggest that the tunable modulator is competitive with conventional bandpass delta-sigma modulators with a fixed passband in terms of the figure of merit (FOM).
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