Hardware implementation of recursive fixed-point filters for minimum quantization noise

Description

Design and implementation of recursive digital filters with f'ixed point arithmetic using special hardware are considered in detail and applied to a mechanization of a second order filter structure with variable coefficients. Two new methods of performing quantization after arithmetic operations within a digital filter are presented: quantization after addition and quantization before multiplication. Both methods are shown applicable to hardware implementation of digital filters and offer advantages over the usual quantization after multiplication. Error bounds are derived for these two quantization schemes and compared with the results previously obtained by other authors. It is concluded that the quantization before multiplication is the most suitable for hardware filter implementation. A design modification of the presently available hardware chips in order to permit round-off or truncation before multiplication is presented.

Subjects

Links

• http://edocs.nps.edu/npspubs/scholarly/theses/1974/Sep/74Sep%5FRodolfo.pdf